1. Field of the Invention
The present invention relates to a technology for large scale integration (LSI) to analyze the highest operation ratio of an LSI in verification of power source design.
2. Description of the Related Art
Greater efficiency through shorter design verification periods is demanded in the design of LSIs; yet verification of proper operation of an LSI is imperative. Verification work is particularly essential for an LSI that is to meet greater demands in scale, function, faster processing speed, and reduced power consumption, while sustaining high quality.
Particularly, in verification of power source design for an LSI, a designer has a desire to confirm that power supply through a designed power line is problem-free even if the LSI shows a highest operation rate. As micro fabrication technology for LSIs progresses, a conventional LSI often has a problem with power supply, a problem that is addressed by the insertion of decoupling capacitors into the LSI.
Currently, however, in many cases, a decoupling capacitor quantity is determined by analysis, independent of simulation or patterns (analysis with the assumption that the entire LSI operates). Hence, suitability of the inserted decoupling capacitor quantity is unclear.
Conventional techniques for verification of power source design have been disclosed and include a simulation or emulation using random number patterns or functional verification patterns (see, e.g., nonpatent document 1: “Full-Chip Verification Methods for DSM Power Distribution Systems”, Design Automation Conference, 1998, pp. 744-749), a static power noise analysis that does not employ patterns (see, e.g., nonpatent document 2: “Pattern Independent Highest Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolutions”, IEEE Translations on Computer-Aided Design, 1995, Vol. 14, No. 8, pp. 998-1012), and a generation of a pattern yielding a highest operation ratio (see, e.g., nonpatent document 3: “Vector Generation for Highest Instantaneous Through Supply Lines for CMOS Circuits”, Design Automation Conference, 1997, pp. 383-388).
With the above conventional verification techniques, however, suitability of the decoupling capacitor quantity is unclear. An insufficient quantity results in functional deficiency, thus degrading the quality of the LSI. To compensate, estimated quantities tend to be increased. However, an excessive quantity leads to a larger chip area, which poses a problem of increased manufacturing cost.
Furthermore, a designer depends on her experience, skill, and intuition in determining a proper decoupling capacitor quantity. As a result, the determined quantity may vary according to designer, thus potentially resulting in reduced quality and increased manufacturing cost.
The conventional technique disclosed in the nonpatent document 1 requires a great deal of time for simulation and emulation, raising a problem of a longer design period. In addition, the technique requires an enormous pattern space, which brings about a problem of difficulty in determining whether a tested operation ratio is large.
The conventional technique disclosed in the nonpatent document 2 features a power noise analysis based on the assumption that the entire LSI operates. Estimated noise volume, therefore tends to be greater, leading to a larger decoupling capacitor quantity and increased chip area, thereby pushing up manufacturing costs.
The conventional technique disclosed in the nonpatent document 3 employs a method of increasing concurrent operation nodes while executing an automatic test pattern generation (ATPG) and an exhaustive solution search by a branch and bound algorithm. This method makes it difficult to obtain the highest operation ratio of an LSI. The technique, therefore, poses a problem of difficulty in verifying whether a power supply problem exists at a highest operation ratio.